The present invention generally relates to data frame processing and more specifically to a circuit configured to process data frames at wire speed.
As frames are transferred through a network, a frame processor validates information in the frame. The format of the information in the frames may be checked for errors. The validation ensures that valid frames are transferred through the network and that a system does not process frames that may cause an error.
In validating data frames, information in the frames is compared to values that should be found in the information. Typically, software code that checks the values of the information using variables in the code. The use of software code to perform the validation of data frames includes many disadvantages. For example, the use of software code may be very time consuming in determining if a data frame is valid. Also, the code is not scalable in that if the speed of data frames being transferred increases, the code cannot be scaled to check the increased data flow. Rather, the amount of data that can be validated remains the same even though more data is being transferred. Thus, bottlenecks may occur when the data flow increases.
The software code may include many conditional branches to perform the validation check. The processing of the conditional branches to validate a data frame may take a large amount of time. Thus, the validation may cause delays in transferring the data frame. Accordingly, software code may not be able to validate data frames in a sufficient amount of time so that data frames can be transferred at wire speed.